The present invention relates generally to semiconductor memory devices, and in particular, the present invention relates to redundancy selection in non-volatile semiconductor memory devices having concurrent read and write capabilities.
Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. In general, memory devices contain an array of memory cells for storing data, and row and column decoder circuits coupled to the array of memory cells for accessing the array of memory cells in response to an external address.
There are several different types of memory. One type is RAM (random-access memory). This is typically used as main memory in a computer environment. RAM refers to read and write memory; that is, you can repeatedly write data into RAM and read data from RAM. This is in contrast to ROM (read-only memory), which generally only permits the user in routine operation to read data already stored on the ROM. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of ROM that holds instructions for starting up the computer. Unlike RAM, ROM generally cannot be written to in routine operation. An EEPROM (electrically erasable programmable read-only memory) is a special type of non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. Many modem PCs have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in modems because it enables the modem manufacturer to support new protocols as they become standardized.
A typical Flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU""s bus and is capable of running at 100 MHZ, about three times faster than conventional FPM (Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. SDRAMs can be accessed quickly, but are volatile. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory.
Memory access speeds can further be improved through the use of concurrent operations. In this manner, the memory device begins performing one operation before a previous operation is completed. Implementation of concurrent operations may introduce problems in redundancy selection.
Redundancy is a method of incorporating spare or redundant devices on a semiconductor die that can be used to replace defective devices. Redundancy is widely used in high density memory devices to improve production yield. As an example, a memory device may have redundant elements, such as redundant memory cells, redundant rows of memory cells or redundant columns of memory cells. If a primary element is determined to be defective, the defective element may be replaced by a redundant element by redirecting the address of the defective element to the redundant element in a manner known in the art. By replacing the defective element, an otherwise unusable memory device becomes commercially acceptable. In devices supporting concurrent operations, selection of a redundant element for a read operation cannot interfere with selection of the redundant element for a write operation, and vice versa.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternate integrated circuits to facilitate selection of redundant elements in semiconductor memory devices having the capability for concurrent read and write operations.
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
Memory devices having redundancy selection circuitry are described herein, with particular reference to synchronous non-volatile memory devices capable of concurrent read and write operations. Such memory devices are suited for high-performance applications. The memory devices include a redundancy comparator for comparing address signals applied to the memory device to known defective address, and for selecting redundant elements if a match is identified. A redundancy comparator includes at least one redundancy compare latch circuit, each redundancy compare latch circuit having a mapping latch circuit, a read address compare circuit coupled to the mapping latch circuit, and a write address compare circuit coupled to the mapping latch circuit. The read address compare circuit and the write address compare circuit thus share the same mapping latch circuit. Such circuits are capable of simultaneously comparing a read address signal and a write address signal, thus facilitating concurrent read and write operations.
For one embodiment, the invention provides a redundancy compare latch circuit. The redundancy compare latch circuit includes a mapping latch circuit coupled to receive and latch a fuse data signal, a read address compare circuit coupled to receive a read address signal and further coupled to the mapping latch circuit to receive the latched fuse data signal, and a write address compare circuit coupled to receive a write address signal and further coupled to the mapping latch circuit to receive the latched fuse data signal. The read address compare circuit provides a read address match signal having a first logic level when the read address signal matches the latched fuse data signal and a second logic level when the read address signal differs from the latched fuse data signal. The write address compare circuit provides a write address match signal having the first logic level when the write address signal matches the latched fuse data signal and the second logic level when the write address signal differs from the latched fuse data signal.
For another embodiment, the invention provides a redundancy compare latch circuit. The redundancy compare latch circuit includes a mapping latch circuit coupled to a first signal node, a second signal node, and a third signal node. The mapping latch circuit is responsive to a first control signal on the first signal node to receive and latch a fuse data signal from the second signal node. The mapping latch circuit is responsive to a second control signal on the third signal node to provide the latched fuse data signal to the second signal node. The redundancy compare latch circuit further includes a read address compare circuit coupled to receive a read address signal and further coupled to the mapping latch circuit to receive the latched fuse data signal. The redundancy compare latch circuit further includes a write address compare circuit coupled to receive a write address signal and further coupled to the mapping latch circuit to receive the latched fuse data signal. The read address compare circuit provides a read address match signal having a first logic level when the read address signal matches the latched fuse data signal and a second logic level when the read address signal differs from the latched fuse data signal. The write address compare circuit provides a write address match signal having the first logic level when the write address signal matches the latched fuse data signal and the second logic level when the write address signal differs from the latched fuse data signal.
For a further embodiment, the invention provides a redundancy compare latch circuit. The redundancy compare latch circuit includes a mapping latch circuit coupled to a first signal node for receiving a first control signal, a second signal node for receiving a second control signal that is a complement of the first control signal, and a third signal node for receiving a fuse data signal. The mapping latch circuit includes a first inverter and a second inverter, wherein the output of the first inverter is coupled to the input of the second inverter. The mapping latch circuit further includes a first pass gate coupled between the third signal node and the input of the first inverter, wherein the first pass gate has a field effect transistor of a first polarity having a gate coupled to the first signal node and a field effect transistor of a second polarity having a gate coupled to the second signal node. The mapping latch circuit further includes a second pass gate coupled between the output of the second inverter and the input of the first inverter, wherein the second pass gate has a field effect transistor of the first polarity having a gate coupled to the second signal node and a field effect transistor of the second polarity having a gate coupled to the first signal node. The redundancy compare latch circuit further includes a read address compare circuit having a first input coupled to a fourth signal node to receive a read address signal, a second input coupled to at least the output of the second inverter, and an output. The read address compare circuit provides on its output a read address match signal having a first logic level when the read address signal matches a logic level at the output of the second inverter and a second logic level when the read address signal differs from the logic level at the output of the second inverter. The redundancy compare latch circuit further includes a write address compare circuit having a first input coupled to a fifth signal node to receive a write address signal, a second input coupled to at least the output of the second inverter, and an output, wherein the write address compare circuit provides on its output a write address match signal having the first logic level when the write address signal matches the logic level at the output of the second inverter and the second logic level when the write address signal differs from the output of the second inverter.
The invention further provides methods and apparatus of varying scope.